The present invention relates to a method for manufacturing an array structure in integrated circuits, and more particularly, to a method for manufacturing an array structure in integrated circuits by selective exposure.
Generally, integrated circuits are mainly divided into two categories: logic device and memory, wherein the logic device, such as a microprocessor of a computer, is used to execute logic operations, and the memory is a semiconductor device used for storing data. Memories can be divided roughly into two categories: read only memory (ROM) and random access memory (RAM).
A ROM comprises a plurality of memory cells for storing data, and each of the memory cells comprises a metal oxide semiconductor (MOS) transistor. The data stored in a ROM does not change in either a power-off condition or a power-on condition, since the data stored in a ROM does not get lost when the power is turned off. The ROM can be distinguished as a mask ROM (MROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM) or an electrically erasable programmable ROM (EEPROM), according to the way for writing the data into the ROM.
MROM is one of the most fundamental ROMs. The method for manufacturing a ROM is first to arrange a plurality of MOS transistors in a matrix format on a die, wherein the MOS transistors are regarded as the memory cells for storing data. Then, a programming step comprises a step of transferring a code pattern layout on a mask onto the ROM, and a step of selectively implanting ions into the designated MOS transistors for disabling the implanted MOS transistors, thereby forming a structure of the ROM. Therefore, this ROM is called Mask ROM, since it is formed from a mask.
Referring to FIG. 1 and FIG. 2, FIG. 1 is a schematic diagram of a conventional binary code pattern layout, and FIG. 2 is a schematic diagram of a mask formed according to the binary code pattern layout shown in FIG. 1. A binary code pattern layout 100 composed of codes xe2x80x9c1xe2x80x9d and codes xe2x80x9c0xe2x80x9d is arranged in a matrix format, and the locations of the codes xe2x80x9c1xe2x80x9d and the codes xe2x80x9c0xe2x80x9d correspond to memory cell regions on a mask 102, i.e. the locations of the codes xe2x80x9c0xe2x80x9d correspond to transparent regions 104 of the mask 102, and the locations of the codes xe2x80x9c1xe2x80x9d correspond to opaque regions 106 of the mask 102.
Referring to FIG. 3 to FIG. 5, FIG. 3 to FIG. 5 are schematic diagrams of a conventional method for writing the binary code pattern layout shown in FIG. 1 into a ROM. As shown in FIG. 3, a ROM 122 is located on a predetermined area of a die 120, and the ROM 122 comprises a plurality of memory cells 124 arranged in a matrix format, wherein each of the memory cells comprises a MOS transistor (not shown). When writing the binary code pattern layout shown in FIG. 1 into the ROM 122, a photoresist layer 126 is first formed and covers on the ROM 122. Then, a mask 102 formed according to the binary code pattern layout 100 is used to perform a photolithography process, so that the patterns on the mask 102 are transferred onto the ROM 122, wherein cell regions of the mask 102 correspond to the memory cells 124 of the ROM 122. Consequently, after the photolithography process, the locations of the memory cells 124 on the ROM 122 corresponding to the locations of the opaque regions 106 of the mask 102 are still covered by the photoresist layer 126, as shown in FIG. 4.
Sequentially, an ion implantation step is performed to implant ions into the memory cells 124 not covered with the photoresist layer 126, so that ion implantation regions 128 are formed, and the remainder of the photoresist layer 126 is removed, as shown in FIG. 5. Since the threshold voltages of the MOS transistors in the ion implantation regions 128 are raised, the MOS transistors in the ion implantation regions 128 have a different threshold voltage. At this time, the ROM 122 matching the binary code pattern layout 100 is completed.
However, with need of increasing device integration, device size continued to be reduced. When an exposing step of a photolithography process is performed with the mask 102, the resolution of a transferred pattern is reduced due to the influence of the optical proximity effect (OPE). In order to enhance the resolution of the transferred pattern, an illuminant having a shorter wavelength is selected to be an exposing illuminant. However, the illuminant having a shorter wavelength would reduce the depth of focus (DOF), so that the code pattern layout on the mask 102 cannot be transferred onto the ROM 122 effectively and successfully, and the binary code pattern layout 100 also cannot be written into the ROM 122.
Currently, another conventional method for writing a set of binary codes into a ROM has been disclosed in the U.S. Pat. No. 6,166,943. By applying this method to write a set of binary codes into a ROM, two masks and two photoresist layers are used to increase the success rate for writing the set of binary codes into the ROM. The two masks mentioned above, however, are all critical masks and the resolution enhancement technologies (RET) have to be used together in the process. The process of manufacturing the two critical masks is very complicated and difficult, so that it takes more time and more costly. In addition, two photoresist layers used in the method not only increases the process time and the complexity of the process, but also increases the cost; as a result, better alternative are required.
According to the aforementioned conventional method for manufacturing an array structure in integrated circuits, transferred patterns having good resolution and sufficient DOF cannot be obtained while writing code patterns into a ROM, so that the codes cannot be written into the ROM successfully. In addition, two masks used in the method introduced to obtain a preferred resolution and a deeper DOF are quite complicated and difficult to be manufactured, and the process for manufacturing the masks needs more cost and time. Thus, the method cannot fill the process needs.
Therefore, one object of the present invention is to provide a method for manufacturing an array structure in integrated circuits. The present invention uses a first mask and a partial dose to perform a first exposing step, and uses a second mask and a compensating dose to perform a second exposing step, so as to fully expose the pattern regions needed to be opened. Hence, the OPE can be reduced, and the resolution can be enhanced, and the DOF can be increased, so that the accuracy for writing codes into a ROM in integrated circuits can be raised.
Another object of the present invention is to provide a method for manufacturing an array structure of a ROM. In the method of the present invention, a first exposing step is performed by using a first mask and a partial exposure dose to partially expose holes of the array structure in a ROM, thereby forming a semi-finished product. After a client""s order is received, a second mask having a desired code pattern is then formed, and used with an exposure dose compensating the insufficient dose in the first exposing step to perform a second exposing step, thereby writing codes into a ROM. With the application of the present invention, the whole process of a ROM is not changed substantially in accordance with the difference of products, and only needs to replace the second mask. Thus, the time for manufacturing a ROM is reduced greatly, and the present invention is very suitable for mass production.
A further object of the present invention is that the usage of photoresist is decreased as to lower the process cost and reduce the process time, because only a photoresist layer is needed in the process for manufacturing an array structure of a ROM.
According to the aforementioned objects, the present invention further provides a method for manufacturing an array structure in integrated circuits, and the method for manufacturing an array structure in integrated circuits is applied in writing an array layout into a ROM in an integrated circuit. In the method, a photoresist layer is first formed to cover the ROM, and a first mask is used to perform a first exposing step on the photoresist layer with a partial exposure dose, so as to transfer the first type cell regions and the second type cell regions on the first mask onto the photoresist layer. On the first mask, a plurality of first type cell regions and a plurality of second type cell regions are formed thereon, and the locations of the first type cell regions and the locations of the second type cell regions correspond to a plurality of memory cells of the ROM. Then, a second mask is used to performing a second exposing step on the photoresist layer with a compensating exposure dose, so as to transfer the array layout on the second mask onto the photoresist layer. On the second mask, the array layout comprising a plurality of first type cell regions and a plurality of second type cell regions is formed thereon, and the locations of the first type cell regions and the locations of the second type cell regions correspond to the memory cells of the ROM. Subsequently, a developing step is performed to remove part of the photoresist layer and to expose part of the memory cells. After the developing step, an ion implantation step is performed to implant a plurality of ions into the exposed memory cells, and then the other part of the photoresist layer is removed to complete the present invention. In another embodiment of the present invention, the ion implantation step can be replaced with an etching step to remove the exposed memory cells.
By using the first mask and the partial exposure dose to perform the first exposing step, and the second mask and the exposure dose compensating the insufficient in the first exposing step to perform the second exposing step, the OPE of the exposing step can be improved, thereby increasing the resolution and the DOF.